Conventionally, obtaining a sub-100 nA micro-power voltage reference for micro-power wide voltage range memory applications required very large matched resistors to achieve a low current, bipolar junction transistors (BJT), and an amplifier to generate a proportional to absolute temperature (PTAT) voltage. FIG. 1 illustrates a circuit schematic for a conventional band-gap voltage reference circuit 100. The large resistors (R1 and R2) are not generally suitable as micro-power components. Furthermore, the use of BJTs 102-106 and resistors R1-R2 introduces BJT mismatch and resistor mismatch.
One purpose of a band gap voltage reference is to balance the negative temperature coefficient of a P-N junction with the thermal voltage (VT, where VT=KT/q). In FIG. 1, the reference voltage Vbg can be expressed as follows:Vbg=Veb106+K1*VT.  (1)The amplifier 108 generates a PTAT voltage across resistor 110 by equalizing nodes A and B. The current through resistor 110 can be expressed as follows:
                                                        I              =                                                Δ                  ⁢                                                                          ⁢                                      V                                          R                      ⁢                                                                                          ⁢                      1                                                                                        R                  ⁢                                                                          ⁢                  1                                                                                                        =                                                                    V                                          eb                      ⁢                                                                                          ⁢                      102                                                        -                                      V                                          eb                      ⁢                                                                                          ⁢                      104                                                                                        R                  ⁢                                                                          ⁢                  1                                                                                                                        =                                                                                                    V                        T                                            ⁢                                              ln                        ⁡                                                  (                                                      I                            /                                                          I                              S                                                                                )                                                                                      -                                                                  V                        T                                            ⁢                                              ln                        ⁡                                                  (                                                      I                                                                                          I                                S                                                            *                                                              K                                2                                                                                                              )                                                                                                                          R                    ⁢                                                                                  ⁢                    1                                                              ,                                                                          =                                                                    V                    T                                    ⁢                                      ln                    ⁡                                          (                                              K                        2                                            )                                                                                        R                  ⁢                                                                          ⁢                  1                                                                                        (        2        )            where the m-factor K2 is equal to 8. Vbg can alternatively be expressed as:Vbg=Veb106+I*R2.  (3)Upon substituting the expression of I from Equation 2 into Equation 3:Vbg=Veb106+R2/R1*ln(8)*VT  (4)Thus, it should be clear from Equation 4 thatK1=R2/R1*ln(K2)  (5)Thus, establishing a band-gap reference voltage in the conventional art depended heavily on the values of R1 and R2.
Beta multiplier voltage references have been developed in the past that do not require the use of a BJT. FIG. 2 is a circuit schematic for one such conventional circuit 200 for generating a beta multiplier voltage reference. When MOSFETS 202-208 operate in the sub-threshold region, the relationship between IDS and VGS depends strongly on Vt variations with respect to temperature. Thus IDS at 90° C. would be greater than IDS at 27° C. On the other hand, when MOSFETS 202-208 operate in the strong inversion region, the relationship between IDS and VGS depends strongly on Mobility (un) variations with respect to temperature. Thus IDS at 90° C. would be less than IDS at 27° C.
FIG. 3 is an IDS vs. VGS curve illustrating a MOSFET's transfer characteristic for two different temperatures. The principle behind beta multiplier voltage references is that there exists a temperature-insensitive value of VGS for a given IDS. This point is denoted as point CP in FIG. 3. However, the temperature insensitivities of circuits such as circuit 200 strongly depend on MOSFET modeling and do not account for threshold voltage and mobility variations with respect to temperature or the variations in resistance. Consequently, these circuits require a significant amount of on-chip trimming.